The present invention generally relates to computer-aided circuit design systems and, more particularly, to a method and apparatus for efficiently evaluating a netlist to determine certain characteristics of circuit elements.
Integrated circuits are electrical circuits comprised of transistors, resistors, capacitors, and other components comprised on a single semiconductor xe2x80x9cchipxe2x80x9d in which the components are interconnected to perform a given function. Typical examples of integrated circuits include, for example, microprocessors, programmable logic devices (PLDs), electrically erasable programmable memory devices (EEPROMs), random access memory devices (RAMs), operational amplifiers and voltage regulators. A circuit designer typically designs the integrated circuit by using very large scale integrated (VLSI) circuit design techniques to create a circuit schematic which indicates the electrical components and their interconnections. Often, designs are simulated by computer to verify functionality and to ensure that performance goals are satisfied.
In the world of electrical device engineering, the design and analysis work involved in producing electronic devices is often performed using electronic computer aided design (E-CAD) tools. As will be appreciated by those skilled in the art, electronic devices include electrical analog, digital, mixed hardware, optical, electro-mechanical, and a variety of other electrical devices. The design and the subsequent simulation of any circuit board, VLSI chip, or other electrical device via E-CAD tools allows a product to be thoroughly tested and often eliminates the need for building a prototype. Thus, today""s sophisticated E-CAD tools may enable the circuit manufacturer to go directly to the manufacturing stage without having to perform costly, time consuming prototyping.
In order to perform the simulation and analysis of a hardware device, E-CAD tools must deal with an electronic representation of the hardware device. A xe2x80x9cnetlistxe2x80x9d is one common representation of a hardware device. As will be appreciated by those skilled in the art of hardware device design, a xe2x80x9cnetlistxe2x80x9d is a detailed circuit specification used by logic synthesizers, circuit simulators and other circuit design optimization tools. A netlist typically comprises a list of circuit components and the interconnections between those components.
The two forms of a netlist are the flat netlist and the hierarchical netlist. Often, a netlist will contain a number of circuit xe2x80x9cmodulesxe2x80x9d which are used repetitively throughout the larger circuit. A flat netlist will contain multiple copies of the circuit modules essentially containing no boundary differentiation between the circuit modules and other components in the device. By way of analogy, one graphical representation of a flat netlist is simply the complete schematic of the circuit device.
In contrast, a hierarchical netlist will only maintain one copy of a circuit module which may be used in multiple locations. By way of analogy, one graphical representation of a hierarchical netlist would show the basic and/or non-repetitive devices in schematic form and the more complex and/or repetitive circuit modules would be represented by xe2x80x9cblack boxes.xe2x80x9d As will be appreciated by those skilled in the art, a black box is a system or component whose inputs, outputs, and general function are known, but whose contents are not shown. These xe2x80x9cblack boxxe2x80x9d representations, hereinafter called xe2x80x9cmodulesxe2x80x9d, will mask the complexities therein, typically showing only input/output ports.
An integrated circuit design can be represented at different levels of abstraction, such as the Register-Transfer level (RTL) and the logic level, using a hardware description language (HDL). VHDL and Verilog are examples of HDL languages. At any abstraction level, an integrated circuit design is specified using behavioral or structural descriptions, or a mix of both. At the logical level, the behavioral description is specified using boolean equations. The structural description is represented as a netlist of primitive cells. Examples of primitive cells include full-adders, NAND gates, latches, and D-Flip Flops.
Having set forth some very basic information regarding the representation of integrated circuits and other circuit schematics through netlists, systems are presently known that use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems are known that perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, generally such systems identify certain critical timing paths, and then evaluate the circuit to determine whether timing violations may occur through the critical paths. As is known, timing specifications may be provided to such systems by way of a configuration file.
One such system known in the prior art is marketed under the name PathMill, by EPIC Design Technology, Inc., subsequently purchased by Synopsis, Inc. PathMill is a transistor-based analysis tool used to find critical paths and to verify timing in semiconductor designs. Using static and mixed-level timing analysis, PathMill processes transistors, gates, and timing models. It also calculates timing delays, performs path searches, and checks timing requirements. As is known, PathMill can analyze combinational designs containing gates, and sequential designs containing gates, latches, flip-flops, and clocks. Combinational designs are generally measured through the longest and shortest paths.
While tools such as these are useful for the design verification process after layout, there are various shortcomings in the PathMill product and other similar products. One primary shortcoming of the PathMill program is that it does not analyze the circuits to determine the design quality of the circuits. Rather, PathMill performs a static timing analysis of a circuit using the netlist provided to PathMill. Furthermore, configuring PathMill to recognize various circuit characteristics is typically a very difficult task.
Accordingly, a need exists for a rules checking system that will allow circuits to be evaluated for design quality. In this regard, xe2x80x9cdesign qualityxe2x80x9d refers to any of a number of tests or checks that may be performed on a circuit. For example, identifying nodes that may be subject to charge sharing, or identifying an excessive number of series-connected pass gates, are examples of circuit checks that may be desired. The present invention may work in conjunction with a tool like PathMill, for example, to build a database which is then utilized by the rules checking system of the present invention to evaluate the design quality of a circuit. Typically, such tools, including PathMill, operate on a netlist to determine FET (field effect transistor) direction, node types, latches, dynamic gates, rise and fall times, etc. This information is utilized by the present invention to build a database which is then utilized by the rules checking system of the present invention to evaluate the design quality of network nodes, preferably of network nodes of FET-level circuits designed in accordance with VLSI techniques.
It should be appreciated that, when evaluating a relatively large netlist for a relatively large number of circuit characteristics, the process may be extremely time consuming and computationally intensive. Accordingly, it is desired to structure and conduct the evaluation in a manner that is highly efficient.
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the advantages and novel features, the present invention is generally directed to a system and method for efficiently evaluating a design quality of a circuit defined by a netlist. In accordance with one aspect of the invention a method is provided for examining a netlist to evaluate a design quality of a circuit. The method includes the steps of creating an element data structure for each circuit element in the netlist, wherein the data structure of a given element defines a plurality of physical characteristics for the element, and creating a node data structure for each circuit node in the netlist, wherein the data structure of a given node defines a plurality of physical characteristics for the node. Thereafter, the method determines a TRUE/FALSE value for the physical characteristics for entries within both the element data structure and the node data structure. Finally, the method records the determined TRUE/FALSE values for later retrieval.
During operation, the method of the preferred embodiment evaluates the design quality of a circuit by determining a number of individual design aspects. The method, in turn, determines each design aspect by evaluating a number of individual physical characteristics of the circuit. For each of these physical characteristics, if the characteristic has been pre-computed and recorded, the method simply retrieves the recorded value for use in the larger evaluation. If, however, the characteristic has not been pre-computed and recorded, the method then computes the characteristic xe2x80x9con the fly.xe2x80x9d
The terms xe2x80x9cdesign qualityxe2x80x9d, xe2x80x9cdesign aspect(s)xe2x80x9d, and xe2x80x9cphysical characteristicsxe2x80x9d have not been chosen for any specific meaning or connotations, but rather have been arbitrarily selected simply to facilitate the description of the invention as set forth herein, and these terms should not be viewed as limiting on the invention. Specifically, the term xe2x80x9cdesign qualityxe2x80x9d is hereinafter used to denote the entire circuit design quality as determined by the electrical rules checker of the present invention. In this regard, the overall design quality is reflected, collectively, by a plurality of design aspects. Each design aspect is, in turn, reflected, collectively, by a plurality of physical characteristics. For example, one design aspect may be whether certain nodes within a circuit are susceptible to a charge sharing phenomenon. Various factors (physical characteristics) may, collectively, be necessary in order to make that determination. For example, a given node may need to be evaluated to determine whether it is an output node.
In accordance with another aspect of the present invention, a method is provided for examining a netlist to evaluate a design quality of a circuit by first identifying a plurality of quality aspects to be evaluated, wherein each quality aspect is defined by at least one physical characteristic. Thereafter, the method selects a group of physical characteristics, from the plurality of physical characteristics to be determined in evaluating the design quality of the circuit. The method determines a TRUE/FALSE value for each physical characteristic of the group of characteristics, and records the determined values for later retrieval. Thereafter, the method evaluates the plurality of quality aspects, using the recorded values of characteristics where appropriate.
In accordance with yet another aspect of the present invention, a system is provided for examining a netlist to evaluate a design quality of a circuit. This system includes an element data structure for defining each circuit element in the netlist, wherein the data structure of a given element defines a plurality of characteristics for the element. The system further includes means for generating TRUE/FALSE value for the characteristics for entries within the element data structure, and means for recording the determined TRUE/FALSE values for later retrieval. During operation, as the system needs the values of various physical characteristics in order to evaluate the design quality of the circuit, the system may simply retrieves the stored values, for each of the relevant physical characteristics. Otherwise, the system computes these values as needed.